Senior Design for Debug DV Engineer

As a Sr. SoC Design Verification Engineer , you will be responsible for Design for Debug (DfD) architecture verification related tasks.

Responsibilities :

Pre-silicon system verification, which includes SoC, FPGA & Full Chip design verification.

Create testcase and testbench with UVM methodology.

Full chip / system functional verification, by defining verification strategies / methodology and test plan to enable effective verification.

Coordinate / interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan.

Experience on Emulation will be an add on.

Qualifications :

At least 6+ years of experience with complex ASIC designs and / or verification.

Familiar with System Verilog language.

Experience on UVM verification methodology, and formal verification method.

Working knowledge of scripting in Linux / Unix environments as well as proficiency in Perl and or Python is desirable.

Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.

Experience with ARM and RISC Debug Architectures is desired with focus on design verification.

Any prior working experience on UltraSoC / Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.

Strong communication skills and the ability to work with a team spread across different geography sites.

Flexible in dynamic environment.

Location : Penang Malaysia or Bangalore India