Design Verification Engineer

Job Description : ASIC Design Verification Engineer

• Location :
• Bangalore, Chennai, Hyderabad, Noida,Malaysia, Germany.
• Experience Range :
• 5 to 20+ years
• Key Responsibilities :
• Develop and execute test plans to verify complex ASIC designs.
• Utilize System Verilog (SV) and UVM methodologies for verification tasks.
• Perform functional, formal, GLS (Gate-Level Simulation), power, and CPU verification.
• Conduct IP and subsystem-level verification, ensuring robust verification of high-speed protocols.
• Work closely with RTL designers to understand design specifications and requirements.
• Write and maintain C / C++ test benches for verification environments.
• Perform coverage analysis and drive coverage closure.
• Debug issues found during verification and work with design teams to resolve them.
• Participate in design and verification reviews, providing insights and suggestions for improvements.
• Develop verification models and ensure their accuracy and performance.
• Qualifications :
• Design Verification Engineer & Junior Verification Engineer :
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 3 years of experience in ASIC design verification.
• Proficiency in System Verilog, UVM, and C / C++.
• Knowledge of functional, formal, GLS, power, and CPU verification methodologies.
• Experience with high-speed protocols and IP verification.
• Strong debugging and problem-solving skills.
• Excellent communication and teamwork abilities.
• Senior Verification Engineer :
• All the qualifications of a Design Verification Engineer.
• Minimum 7 years of experience in ASIC design verification.
• Demonstrated leadership in verification projects.
• Strong experience in subsystem-level verification and high-speed protocols.
• Proven track record in coverage closure and verification planning.
• Lead Verification Engineer :
• All the qualifications of a Senior Verification Engineer.
• Minimum 10 years of experience in ASIC design verification.
• Extensive experience leading verification teams and projects.
• Expertise in multiple verification methodologies and high-speed protocols.
• Strong project management and leadership skills.
• Senior Lead Verification Engineer :
• All the qualifications of a Lead Verification Engineer.
• Minimum 12 years of experience in ASIC design verification.
• Experience in managing large verification projects and multiple teams.
• Expertise in formal, functional, GLS, power, and CPU verification.
• In-depth knowledge of verification models and techniques.
• Staff Engineer :
• All the qualifications of a Senior Lead Verification Engineer.
• Minimum 15 years of experience in ASIC design verification.
• Significant experience in driving and mentoring large verification teams.
• Recognized as an industry expert in verification methodologies and high-speed protocols.
• Strong strategic vision and ability to influence product development.
• Preferred Skills :
• Experience with different models of a product.
• Familiarity with advanced verification tools and environments.
• Ability to handle multiple tasks and projects concurrently.
• Strong interpersonal and communication skills.
• Demonstrated ability to mentor and train junior engineers.
• Benefits :
• Competitive salary and benefits package.
• Opportunity to work on cutting-edge technology and projects.
• Professional development and career advancement opportunities.
• Collaborative and innovative work environment.
• How to Apply :

Interested candidates should send their resume and cover letter to sushma.siddaroda@tessolve.com Please specify the position you are applying for in the subject line