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IP Verification Lead - System Verilog

IP Verification Lead - System Verilog

Akshaya IT Business solutionsBangalore
27 days ago
Job description

Designation : IP Verification Lead

Experience : 7+ Years

We are seeking a highly experienced and technically adept IP Verification Lead to join our dynamic engineering team. The ideal candidate will be a seasoned professional with a strong background in SystemVerilog and UVM, possessing the ability to define robust verification strategies and architect complex test benches from the ground up. This role offers the opportunity to lead verification efforts across multiple projects, guide junior engineers, and contribute significantly to the delivery of high-quality IP.

Key Responsibilities :

  • Define and drive the overall verification strategy for complex IP designs, ensuring comprehensive test coverage and adherence to quality standards.
  • Architect and develop verification test benches from scratch using advanced verification methodologies, primarily SystemVerilog (SV) and Universal Verification Methodology (UVM).
  • Lead the entire verification cycle for IP projects, from test plan creation and environment development to test execution, debug, and coverage closure.
  • Demonstrate a proven track record of successfully completing the full verification cycle in more than one significant project.
  • Provide technical leadership, mentorship, and guidance to junior verification engineers and team members, fostering their growth and ensuring project success.
  • Collaborate effectively with design, architecture, and software teams to understand design specifications and translate them into robust verification plans.
  • Develop and maintain automation scripts and utilities using Perl or Python to enhance verification efficiency and productivity.
  • Present verification plans, progress, and results clearly and concisely to internal and external stakeholders, demonstrating excellent presentation skills.
  • Analyze functional and code coverage data to identify gaps and drive verification closure.
  • Debug complex design and verification issues, identifying root causes and proposing effective solutions.
  • Contribute to the continuous improvement of verification methodologies, flows, and best practices.

Required Skills & Qualifications :

  • Experience : 7+ years of experience in IP or SoC verification.
  • Verification Expertise : Extensive hands-on experience with SystemVerilog (SV) and Universal Verification Methodology (UVM).
  • Test Bench Architecture : Proven ability to define verification strategies and independently architect and develop verification test benches from scratch.
  • Verification Cycle : Demonstrated experience in leading and completing the full verification cycle across multiple projects.
  • Leadership & Mentorship : Strong ability to guide, mentor, and technically lead junior resources.
  • Scripting Skills : Proficiency in scripting languages, specifically Perl or Python, for automation and verification flow development.
  • Debugging Skills : Strong debugging and problem-solving skills for complex hardware and software interactions.
  • Communication : Excellent written and verbal communication skills, including strong presentation abilities, for technical discussions and stakeholder updates.
  • Collaboration : Ability to work effectively in a collaborative team environment and engage with cross-functional teams.

    • ref : hirist.tech)

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