Tecquire Solutions - RTL Engineer - System Verilog

Job Summary :

We are looking for an experienced Senior RTL Design Engineer with a strong background in SoC architecture, logic design, and RTL development. This role is ideal for candidates who are passionate about software-driven digital hardware design and have in-depth knowledge of modern SoC systems, protocols, and low-power design Responsibilities :

• Design and implement scalable RTL architectures for complex SoC components using Verilog / SystemVerilog.
• Develop and maintain logic blocks aligned with architectural and functional specifications.
• Collaborate with design verification and architecture teams to define module interfaces and performance metrics.
• Implement low-power design techniques using software methodologies such as clock gating, power domain partitioning, etc.
• Model asynchronous interfaces and multi-clock domain logic for integration into larger SoC platforms.
• Analyze design performance and optimize RTL for area, power, and logical efficiency.
• Write clean, reusable, and synthesis-friendly RTL code following best practices and coding standards.
• Simulate and debug logic design using industry tools and waveform analysis.
• Integrate IPs and subsystems in a modular and maintainable way using software configuration and scripting Skills & Experience :
• 5+ years of experience in RTL design, logic development, and micro-architecture.
• Strong command over Verilog / SystemVerilog and digital design methodologies.
• Proven experience in designing software-driven SoC architectures with modular, configurable

RTL.

components.

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