Role Overview :
As a Physical Design Engineer, you will be responsible for implementing and optimizing the physical layout of digital blocks and full-chip designs, ensuring they meet performance, power, area (PPA), and manufacturability targets. You will collaborate closely with cross-functional teams to deliver high-quality silicon solutions that meet customer requirements and industry standards.
Key Responsibilities :
- Netlist to GDSII Implementation : Lead the physical design flow from gate-level netlist to GDSII, including floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, static timing analysis (STA), power integrity analysis, and physical verification.
- Tool Proficiency : Utilize industry-standard EDA tools such as Synopsys Innovus, ICC2, Primetime, PT-PX, and Mentor Calibre to perform design implementation and signoff tasks.
- Design Methodologies : Apply physical design methodologies for submicron technology nodes (28nm and below), ensuring optimal performance, power, and area metrics.
- Scripting : Develop and maintain scripts in languages like Tcl, Perl, or Python to automate design tasks and improve efficiency.
- Timing Closure : Ensure timing closure across various process corners and operating conditions, addressing setup and hold violations.
- Power Integrity : Analyze and resolve issues related to power distribution, signal integrity, and noise, ensuring robust power delivery networks.
- Physical Verification : Perform design rule checking (DRC), layout versus schematic (LVS) checks, antenna rule checking (ARC), and electrical rule checking (ERC) to ensure compliance with manufacturing requirements.
- Collaboration : Work closely with RTL design, verification, DFT, and software teams to address design challenges and ensure seamless integration.
- Documentation : Create and review design documents, including specifications, test plans, and integration guides.
Mandatory Qualifications Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or a related 7+ years of experience in physical design and implementation of digital ICs.
Technical Skills :
In-depth knowledge of the ASIC physical design flow from gate netlist to GDSII.Hands-on experience with EDA tools : Synopsys Innovus, ICC2, Primetime, PT-PX, Mentor Calibre.Strong understanding of STA, power integrity analysis, and physical verification.Proficiency in scripting languages : Tcl, Perl, or Python.Experience with submicron technology nodes (28nm and below).Soft Skills :
Strong problem-solving and debugging abilities.Excellent communication and collaboration skills.Ability to work effectively in a team-oriented environment.ref : hirist.tech)