Senior design verification engineer (design for debug)

Job Description :

As a Sr. So C Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and / or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.

Responsibility

Pre-silicon system verification. This include So C, FPGA & Full Chip design verification.

Create testcase and testbench with UVM methodology

Fullchip / system functional verification, by defining verification strategies / methodology and test plan to enable effective verification

Coordinate / interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan

Experience on Emulation will be an add on.

Qualifications :

6+ years of experience with complex ASIC designs and / or verification

Familiar with System Verilog language

Experience on UVM verification methodology, and formal verification method

Working knowledge of scripting in Linux / Unix environments as well as proficiency in Perl and or Python is desirable.

Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.

Experience with ARM and RISC Debug Architectures is desired with focus on design verification.

Any prior working experience on Ultra So C / Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.

Strong communication skills and the ability to work with a team spread across different geography sites

Flexible in dynamic environment

Contact : Ms. Anna - Whats App

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