Principal Design Verification EngineerACL Digital • Hyderabad, Republic Of India, IN
Principal Design Verification Engineer
ACL Digital • Hyderabad, Republic Of India, IN
30+ days ago
Job description
🔹 Solid experience in SystemVerilog / UVM
🔹 PCIe protocol verification expertise
🔹 Strong understanding of IP-level protocols
🔹 Hands-on with DV environments, debugging & coverage
🔹 Ability to work across design, architecture & validation teams
#ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog #PCIe #VLSICareers #HyderabadJobs #BangaloreJobs
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Design Verification Engineer • Hyderabad, Republic Of India, IN
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