Principal IP / RTL Design Engineer for TPU

Principal IP / RTL Design Engineer for TPU

Hyderabad / Bangalore

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad / Bangalore

IP / RTL Design Engineer for TPU

Position Overview

Seeking an IP / RTL Design Engineer with 5+ years of experience to design IP / RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration.

Key Responsibilities

• Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems.
• Develop Verilog / SystemVerilog RTL for performance, timing, and area optimization.
• Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines.
• Optimize designs for high throughput, low latency, and power efficiency in AI workloads.
• Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces.
• Support synthesis, timing closure, and FPGA prototyping and Design Verification team
• Document microarchitecture and design specifications.

Required Qualifications

Preferred Qualifications

What is in it for you?

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

Mining The Knowledge Community"