Senior Layout Design Engineer

BoltChip builds Global Capability Centres (GCCS) for semiconductor IC Design and AI innovation companies in ASIA

Role : Senior Layout Engineer – TSMC 12nm and Below

Location : Gujarat

Experience : 5+ years

Industry : Semiconductor Design

About the Role :

We are seeking an experienced Senior Layout Engineer to join our semiconductor design team. This role is ideal for professionals with a solid background in deep sub-micron technologies and hands-on experience in analog layout, particularly with TSMC 12nm and below process nodes.

Key Responsibilities :

• Execute full custom layout for analog and mixed-signal blocks including IO (TX and RX), PLLs , and other analog circuits.
• Ensure high-quality layout design aligned with DRC, LVS, and EMIR compliance using industry-standard tools.
• Collaborate closely with circuit design teams and physical verification engineers to resolve layout issues.
• Participate in design reviews and contribute to layout planning and optimization.
• Maintain quality and performance standards in high-speed, low-power layout design.

Required Qualifications :

Preferred Qualifications :

Why Join Us?

Be part of a fast-growing semiconductor design group working on cutting-edge technology. You’ll collaborate with some of the sharpest minds in the industry and help shape the future of SoC innovation.