SoC Verification Lead - Embedded Testing

SoC NoC Verification Lead with 10+ years of experience

Seeking someone who has experience in developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems.

Key Responsibilities :

• Lead verification efforts for IP / sub-systems and full-chip SoC and NoC architectures.
• Define comprehensive verification plans : scope, test cases, coverage goals, assertions, corner-case scenarios.
• Architect and maintain robust, reusable, and scalable UVM / SystemVerilog environments with BFMs, monitors, scoreboards, and reference models-
• Develop assertion-based checks and functional coverage metrics using SVA.
• Implement performance, power-aware, and gated-level verification flows (including UPF-based flows)-
• Integrate, configure, and debug verification IPs for protocols like AXI, CHI, PCIe, Ethernet, CXL, UCIe, DDR-
• Debug RTL, gate-level, and emulation failures using tools like Verdi, SimVision, waveform analyzers-
• Collaborate with RTL designers, architects, DFT, firmware, emulation, and post-silicon teams to ensure clean design handoffs and first-time-right silicon-
• Mentor verification engineers and foster team best practices in testbench quality and automation-
• Track and report key verification metrics (functional / code coverage, power, performance) and drive toward verification closure.
• Enhance verification methodologies with tools for CI / CD, FPGA prototyping, portable stimulus, or formal techniques- .

Required Skills & Qualifications :

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