STA Characterization Engineer

Job Title : STA Characterization Engineer

Location : Hyderabad

Job Type : Full-time

Experience Level : 2–8 years

Department : VLSI / Physical Design / Timing Analysis

Job Summary :

We are seeking a highly skilled STA Characterization Engineer to join our VLSI design team.

The ideal candidate will have strong experience in Static Timing Analysis (STA), library characterization, and timing model generation across PVT corners.

This role involves close collaboration with RTL, physical design, and library development teams to ensure accurate and efficient timing models for digital designs.

Key Responsibilities :

Perform characterization of standard cells, IOs, and custom macros for timing, noise, and power.

Generate and validate Liberty (.lib) timing models across multiple PVT corners.

Run Static Timing Analysis (STA) using tools like PrimeTime or Tempus and perform timing model correlation.

Analyze and debug timing violations, noise margins, and signal integrity issues.

Develop and maintain timing constraints (SDC) files for STA runs.

Work closely with library / IP teams to ensure accurate timing and integration of cells into the physical design flow.

Develop automation scripts (Tcl, Python, Perl) to streamline STA and characterization workflows.

Evaluate and document the impact of process, voltage, and temperature (PVT) variations.

Collaborate with physical design and synthesis teams to meet timing closure and signoff requirements.

Required Qualifications :

Bachelor's or Master’s degree in Electrical Engineering, Electronics, VLSI, or related fields.

2+ years of experience in STA, timing model development, or library characterization.

Hands-on experience with STA tools such as Synopsys PrimeTime, Cadence Tempus, or equivalent.

Familiarity with .lib format, SDF, and delay calculation principles.

Solid understanding of digital design concepts, timing arcs, setup / hold violations, and signal integrity.

Experience in scripting languages such as Tcl, Perl, Python, or Shell scripting.

Knowledge of PVT variation handling and multi-mode, multi-corner (MMMC) analysis.

Preferred Qualifications :

Experience with standard cell characterization tools like Liberate, SiliconSmart, or Characterization Tools from Synopsys / Cadence.

Understanding of low-power design techniques and multi-Vt cell libraries.

Familiarity with EDA flows in advanced technology nodes (7nm, 5nm, 3nm).

Exposure to Liberty Validation Tools, NLDM / CCS / AOCV / LVF models.

Prior experience with ECO timing validation and timing signoff flows.