RTL ASIC Front end Design Engineer / Lead

Hi All, we are hiring RTL Engineer and Lead with Tessolve Semiconductors - Bangalore and Hyderabad.

Please find the below JD.

JD- 1 ( 5- 8 yr) RTL ASIC front end design with Microarchitecture and Verilog coding . MAS development RTL coding Development of module, feature addition Experience in Medium complexity protocol Well familiar in slow speed protocols like I2C / SPI / UART Familiar in AMBA bus protocols (APB, AHB, AXI) Has experience in Quality check flows (Lint / CDC)

JD - 2 for 8+ yr Exp Very strong in RTL coding Micro-Architechture (uArch) development Owned and delivered a Sub-system, Top level in a SoC project Has expertise in IP design, Sub-system design , SoC integration Has successfully lead a team of engineers and completed the deliverables on time

Kindly share your updated CV to

gayatri.kushe@tessolve.com

or connect on

6361542656,

And Refer

Disclaimer :

At Tessolve, we are committed to fostering a workplace that embraces and celebrates diversity in all its forms. We believe that diverse teams drive innovation, creativity, and success. We are dedicated to creating an inclusive environment where all employees, regardless of their race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status, feel valued and respected. We believe in fair and equitable treatment for all employees and aim to eliminate any biases or barriers that may hinder personal or professional growth.