Dft Engineer

Experience : 10–15 Years

We are looking for a highly experienced DFT Engineer with strong expertise in Mentor Graphics Tessent tools. The candidate should have deep hands-on experience across the full DFT flow—implementation, validation, debug—and be able to work independently on complex SoC designs.

Key Responsibilities

• Perform RTL insertion , DFT DRC checks , and debug using Tessent tools.
• Execute scan insertion , ATPG pattern generation , and coverage validation .
• Conduct gate-level simulation (GLS) debug, including timing-enabled GLS .
• Generate and validate MBIST patterns for memory test.
• Independently debug and resolve DFT issues across the SoC.
• Collaborate with cross-functional engineering teams to address design and test challenges.
• Ensure high quality and coverage of DFT implementation.

Essential Requirements (Must-Have)