Functional Verification Engineer

Project Description :

We are seeking an experienced Functional Verification Engineer with strong expertise in System Verilog / UVM to develop and maintain verification environments for block-level and IP-level designs. The ideal candidate will be proactive, self-driven, and capable of managing deliverables independently.

Responsibilities :

• Develop and maintain block-level verification environments and testbenches using SystemVerilog / UVM.
• Create and execute verification plans (VPlans), run regressions, and drive coverage closure.
• Implement and verify designs using real number modeling (RNM) for mixed-signal interfaces.
• Perform netlist and gate-level simulations (GLS) to validate post-synthesis and post-layout functionality.
• Debug functional and testbench issues, ensuring high-quality, reusable verification components.

Mandatory Skills Description :

Nice-to-Have Skills Description :