About Cadence :
Cadence is a global leader in electronic design automation, known for driving innovation across semiconductors, systems, and AI-driven computing platforms. With over three decades of computational software expertise, Cadence delivers advanced technologies that enable our customers to build extraordinary electronic products.
Role Overview :
We are seeking a highly motivated and technically strong Lead Analog Design Engineer to drive the design and development of high-speed PHY IPs such as USB3, PCIe, DPHY, and more. You will be a key contributor in the analog design domain and participate in the full lifecycle of IP developmentfrom specification to silicon validation. This role also involves collaboration with layout, digital, and system-level teams, along with customer-facing engagements.
Key Responsibilities :
- Lead and contribute to the design of high-speed analog / mixed-signal IPs including PLLs, data converters, and high-speed serial interfaces (USB3, PCIe, MIPI DPHY, etc.)
- Own and execute full custom analog design including transistor-level schematic design, simulation, verification, and silicon debug
- Collaborate closely with layout engineers to ensure optimal layout and performance of the analog blocks
- Support physical design and post-layout validation, ensuring compliance with power, performance, and area (PPA) targets
- Perform integration of analog IPs into larger SoC environments and validate at chip level
- Participate in silicon characterization, debug, and bring-up on ATE or lab platforms
- Document design specifications, simulation results, test plans, and silicon results
- Interface with cross-functional teams including digital, software, validation, and application engineers to deliver robust and production-quality IPs
- Engage in technical discussions with customers to understand requirements, support integration, and resolve post-silicon issues
Technical Requirements :
Bachelors or Masters degree (B.Tech / M.Tech / BE / ME) in Electrical or Electronics Engineering from a reputed institutionMinimum 4 years of hands-on experience in analog / mixed-signal IC designProven experience in designing and delivering IPs such as :
PLLs, LDOs, Bandgap References, SerDes, ADCs / DACsHigh-speed interfaces like PCIe Gen2 / 3 / 4, USB2 / 3, MIPI DPHYStrong understanding of transistor-level design, device physics, and analog circuit behaviorProficient with industry-standard EDA tools such as Cadence Virtuoso, Spectre, HSPICE, and CalibreExperience with full-chip floor planning, IR drop analysis, EM / ESD verification is desirableFamiliarity with lab measurement tools like oscilloscopes, BERTs, and spectrum analyzersExperience in silicon debug and post-silicon validationref : hirist.tech)