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Lead CPU Architecture and Logic design Engineer

Lead CPU Architecture and Logic design Engineer

Mulya TechnologiesGreater Bengaluru Area, India
4 days ago
Job description

Lead Processor Architecture and Logic design Engineer

Fortune 100 Organization

Location : Bangalore

Introduction

As a Hardware at , you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today’s market.

Your Role And Responsibilities

  • Lead the Architecture, Design and development of processor L2 and LLC (Last Level

Cache) for high-performance Systems.

  • Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS
  • requirements.

  • Develop the features, present the proposed architecture in the High level design
  • discussions

  • Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical
  • design, FW, SW teams to develop the feature

  • Signoff the Pre-silicon Design that meets all the functional, area and timing goals
  • Participate in silicon bring-up and validation of the hardware
  • Lead a team of engineers, guide and mentor team members, represent as Logic Design
  • Lead in global forums.

  • Estimate the overall effort to develop the feature.
  • Estimate silicon area and wire usage for the feature
  • Preferred Education

    Master's Degree

    Required Technical And Professional Expertise

  • 12+ years of relevant experience
  • At least 1 generation of processor L2 cache or LLC design delivery leadership.
  • Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering
  • both chip SMP and multi-socket SMP.

  • Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures
  • and implementations.

  • Working knowledge of memory consistency, store ordering, weakly and strongly ordered
  • memory.

  • Experience in logical and physical design of caches including directories (tags, set
  • associative memories), data SRAM, design for low latency, multiple parallel finite state

    machine design, deadlock-free designs.

    Contact : Uday

    Mulya Technologies

    muday_bhaskar@yahoo.com

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    Design Lead • Greater Bengaluru Area, India