ASIC Timing Closure Engineer

essolve – STA Engineer (4+ Years Experience)

Location : Bangalore

Job Type : Full-Time

Experience : 4–8 years

Domain : ASIC / SoC – Static Timing Analysis

Job Summary

Tessolve is seeking a skilled STA Engineer with 4+ years of hands-on experience in block-level and / or chip-level timing analysis and closure. The ideal candidate should be proficient with industry-standard timing tools, sign-off methodologies, and timing constraints development for advanced technology nodes.

Key Responsibilities

Static Timing Analysis & Closure

• Perform block-level and top-level STA using Synopsys PrimeTime or equivalent sign-off tools.
• Develop, validate, and maintain timing constraints (SDC) for functional and test modes.
• Analyze and resolve setup, hold, DRV, SI / Noise , and cross-corner timing issues .
• Drive timing closure by coordinating with RTL, physical design, DFT, and architecture teams.

Timing Sign-Off & Debug

Tool & Flow Expertise

Required Skills & Experience